1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to a semiconductor device comprising a multi-layer channel region and various methods of forming such a semiconductor device.
2. Description of the Relate Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFET or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A conventional FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above or around the channel region. Drive current through the FET is controlled by setting the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is stimulated to flow between the source region and the drain region through the conductive channel region. To improve the operating speed of conventional FETs, device designers have significantly reduced the channel length of such devices, which has resulted in improving the switching speed and in lowering operation currents and voltages of FETs. However, decreasing the channel length of a FET also makes it difficult to control the channel region of the device. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device 10 includes a plurality of trenches 14 that define three illustrative fins 16, a cladding material 17 (see FIG. 1B) formed on the fin 16, a gate structure 18, sidewall spacers 20 and a gate cap layer 22. The fins 16 have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L of the fins 16 corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 16 covered by the gate structure 18 are the channel regions of the FinFET device 10. FIG. 1B is a cross-sectional view of the FinFET device 10 taken through the gate structure 18 in a gate width direction of the device 10. The gate structure 18 is typically comprised of a layer of gate insulating material 18A (see FIG. 1B), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal, metal alloy, metal stack and/or polysilicon) that serve as the gate electrode 18B (see FIG. 1B) for the device 10. In the device 10, the cladding material 17 is the primary current carrying portion of the channel region when the device 10 is operational. Typically, with respect to current day technology, the cladding material 17 may have a thickness of about 2-3 nm. The cladding material is typically an epic semiconductor material, such as silicon germanium, that is formed on the fin 16 by performing known epic deposition processes.
As shown in FIG. 1C, one process flow that is typically performed to form the illustrative FinFET device 10 with the cladding material 17 positioned on the fin 16 is as follows. First, a plurality of trenches 14 were formed in the substrate 12 to define the initial fins 16 (only one fin is shown in FIG. 1C). After the trenches 14 are formed, a layer of insulating material 24, such as silicon dioxide, was formed so as to overfill the trenches 14. Thereafter, a chemical mechanical polishing (CMP) process was performed to plagiarize the upper surface of the insulating material 24 with the top of the fins 16 (or the top of a patterned hard mask). Thereafter, a recess etching process was performed to recess the layer of insulating material 24 between adjacent fins 16 so as to thereby expose the upper portion of the fin 16. At this point, an epitaxial deposition process was performed to form the cladding material 17 on the exposed portion of the fin 16. Additional steps are then performed to complete the fabrication of the device, i.e., gate formation, sidewall spacer formation, epic material growth in the source/drain regions of the device, etc.
While the above-described process flow has worked well for current technology nodes, the use of such methodologies in future device generations is problematic. More specifically, with reference to FIG. 1B, the fin 16 may have a width 16W on the order of about 30 nm or so and it may be readily manufactured using currently available tools and techniques. If the cladding material 17 has a thickness of about 3 nm, then, in this example, the overall width 21 of the channel structure may be about 36 nm. With reference to FIG. 1C, as device dimensions are continually reduced for future technology nodes, the overall allowable width 19 of the channel structure may be limited to about 10 nm, and the height 16H of the fin 16 may need to be about 24 nm or so to provide sufficient drive current and insure high drive current densities. With the thickness 17T of the cladding material 17 being about 3 nm (or 4 nm), that means that the fin 16 will have to be initially manufactured to a thickness 16T of about 4 nm (or 2 nm) to maintain the overall target width 19 of about 10 nm. Manufacturing such a relatively tall and slender fin 16 is very difficult to do using the process flow described above. One possible solution that might help to alleviate this problem would be to decrease the thickness 17T of the cladding material 17, but that would increase the resistance in the channel region and be counter-productive to the primary purpose of forming the channel cladding material 17 in the first place.
The present disclosure is directed to various embodiments of a semiconductor device comprising a multi-layer channel region and various methods of forming such a semiconductor devices that may reduce or eliminate one or more of the problems identified above.